Objectives in CMOS receiver design include optimization of receiver performance, such as gain, bandwidth and noise margin within the receiver; power consumption reduction; and receiver versatility for use in different applications. With regards to performance optimization, gain and bandwidth values are generally interdependent, where optimization of gain compromises bandwidth, and vice versa. For given operating conditions, such as temperature and power supply level, the gain and bandwidth product is typically constant. With regards to power consumption, power reduction may negatively affect performance.
With regards to receiver versatility, a receiver having one design may be used with different applications that may have different specifications, such as frequency and amplitude, for expected incoming signals. While design costs are reduced, and only a single set of design library files and photo-masks need be generated and maintained, performance and power consumption may be compromised. For example, one receiver may need to be capable of operating with incoming signals that have a large range of frequency.
In order for the receiver to operate with a high frequency incoming signal its bandwidth must be boosted. However when using the same receiver for an application in which the incoming signal has a lower frequency, the receiver will typically consume more power than necessary, the gain of the receiver may not be optimized, and the jitter noise margin may not be optimized either. Furthermore, for applications in which the amplitude of the incoming signal is low, optimization of gain is critical, even for applications in which the incoming signal has a low frequency.
A tunable receiver may be used to overcome the above problems, where the receiver is tuned in accordance with the operating conditions for optimizing the receiver's performance and minimizing power consumption. One suggested receiver is described in U.S. Pat. No. 5,864,416, by Williams, entitled “TUNING OPTICAL COMMUNICATIONS RECEIVER BY CONTROLLING DRAIN CURRENT INPUT TO VARIABLE TRANSCONDUCTANCE FET STAGE OF VARIABLE BANDWIDTH TRANSIMPEDANCE AMPLIFIER”. However, the described receiver is designed using BiCMOS technology for receiving optical single-ended incoming signals. The bandwidth of the receiver is adjusted by using a variable transconductance device by continuously monitoring the incoming pulse frequency. A heterojunction field effect transistor HJFET is used, whose transconductance exhibits a non-linear relationship with drain current over the operational bandwidth. This method is not applicable for low-power CMOS integration. Furthermore, size and power consumption of BiCMOS circuits are relatively high compared to CMOS circuits.
Another tunable receiver is described in U.S. Pat. No. 5,852,637 by Brown et al., entitled “SERIAL MULTI-GB/S DATA RECEIVER”. However, the described receiver is also designed using BiCMOS technology. The circuit is complex, since for each receiver an extra monitoring receiver and associated bias generator, and a pulse height detector circuits are needed. Thus, the size and power consumption are relatively large compared to a receiver having CMOS circuits.
Accordingly, a need exists for a relatively small and low power tunable receiver in which the gain and bandwidth of the receiver are selectable.
Furthermore, a need exists for a system and method to tune a CMOS receiver by tuning the gain via variable load resistors of stages of the receiver.
A need further exists for a system and method to tune a CMOS receiver by tuning the gain via an adjustable bias current generator.
In addition, a need exists for a system and method to tune a CMOS receiver by selecting the gain and bandwidth of the receiver during a power-on period.
Finally, a need exists for a system and method to tune a CMOS receiver by selecting the gain and bandwidth of the receiver during a operation of the receiver via a feedback control circuit in response to sensed temperature, supply voltage and incoming data rate.